Trench-gate semiconductor device and method of manufacturing

ABSTRACT

Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.

The present invention relates to trench-gate semiconductor devices, forexample insulated-gate field effect power transistors (commonly termed“MOSFETs”), or insulated-gate bipolar transistors (commonly termed“IGBTs”).

Such trench-gate semiconductor devices are known having a source regionand a drain region of a first conductivity type which are separated by achannel-accommodating region adjacent to the gate. U.S. Pat. No.5,998,833 describes a vertical device of this type which includes atrench-based source electrode, between the gate electrode and the bottomof the trench. The trench-based source electrode is electricallyconnected to the source electrode of the device. It is provided with aview to improving the breakdown and high frequency switchingcharacteristics of the device with minimal impact on its specificon-state resistance.

EP-A-1170803 discloses a similar structure to that referred to above inrelation to U.S. Pat. No. 5,998,833. A “shield gate” is located belowthe gate electrode, near the bottom of the trench. In particular, itdescribes a device in which the shield gate is connected to the sourceregion. The contents of U.S. Pat. No. 5,998,833 and EP-A-1170803 arehereby incorporated herein as reference material.

It is an object of the present invention to provide an improved methodfor manufacturing a trench-gate semiconductor device having a trenchedelectrode below the gate.

The present invention provides a method of manufacturing a trench-gatesemiconductor device, the device including a semiconductor body defininga first portion of a trench having an insulated gate therein, a secondportion of the trench extending from the bottom of the first trenchportion, the semiconductor body comprising a source region and a drainregion of a first conductivity type which are separated by achannel-accommodating region adjacent to the first trench portion, thedrain region comprising a drain drift region and a drain contact region,with the drain drift region between the channel-accommodating region andthe drain contact region, and the drain drift region doped to a lesserextent than the drain contact region, and a field plate in the secondportion of the trench between the gate and the drain contact region, themethod including the steps of:

(a) etching a first groove into the semiconductor body;

(b) forming spacers adjacent the sidewalls of the first groove whichdefine a window therebetween;

(c) etching a second groove into the semiconductor body through thewindow between the spacers, the second groove extending from the bottomof the first groove towards the drain contact region and being narrowerthan the first groove; and

(d) forming a field plate insulating layer by oxidising the bottom andsidewalls of the second groove.

In the above process, the vertical extent of the field plate insulatinglayer is self-aligned with the bottom of the first groove owing to thepresence of the spacers. This ensures greater uniformity in the devicestructure in its manufacture.

In contrast, in the process shown in U.S. Pat. No. 5,998,833 forexample, the vertical extent of the insulating layer around thetrench-based source electrode is defined by the end point of an etchback step which is not self-aligned with the rest of the structure.

In a preferred embodiment, a method of the invention includes the stepsof:

(e) providing the field plate over the field plate insulating layer inthe second groove by filling the first and second grooves with electrodematerial and etching it back until the field plate insulating layer isexposed;

(f) removing the spacers;

(g) forming a gate insulating layer over the field plate and at thebottom and sidewalls of the first groove; and

(h) providing the gate over the gate insulating layer.

Thus, the etching back of the field plate electrode has a clearlydefined end point, namely the exposure of the upper surface of the fieldplate insulating layer. The upper extent of the field plate may therebybe reliably and reproducibly aligned with the bottom of the firstgroove. Exposure of the field plate insulating layer may be detectedusing well known spectrometry techniques.

According to an alternative preferred embodiment, a method of theinvention includes the steps of:

(i) removing the spacers;

(j) forming a gate insulating layer over the bottom and sidewalls of thefirst groove; and then

(k) filing the first and second grooves with electrode material to formthe gate and field plate.

The invention further provides a trench-gate semiconductor devicemanufactured according to a method as described herein, in which thewidth of the first trench portion is greater than the width of thesecond trench portion.

In embodiments where the field plate is insulated from the gate, thefield plate may be connected to the source region. Alternatively, it maybe connected to a bias potential greater than the gate potential andnear to the bulk breakdown voltage of the drain drift region. A devicehaving a field plate connected in this way and a method for itsmanufacture are described in the applicant's copending United KingdomPatent Application No. 0212564.9 (our ref. PHGB020083), the contents ofwhich are incorporated herein by reference.

The inventors have realised that connection of such an insulated fieldplate to a potential close to the bulk breakdown voltage of the draindrift region causes the potential drop across the drain drift region tobe spread considerably more evenly particularly at applied voltagesgreater than the bulk breakdown voltage, thereby substantiallyincreasing the breakdown voltage of the device. This enables a higherlevel of doping to be used in the drain drift region relative to adevice without the field plate having the same breakdowncharacteristics, thereby providing devices with a lower specificon-state resistance.

The present invention also provides a module comprising a device havinga configuration defined above along with one or more other semiconductordevices, wherein the field plate is conveniently connected to aninternal voltage line of the module. Alternatively, an additionalexternal terminal may be provided on the device (in the case of adiscrete device) or the module which is electrically connected to thefield plate. This enables a dedicated voltage level for the field plateto be applied.

Embodiments of the invention will now be described by way of example andwith reference to the accompanying schematic drawings, wherein:

FIGS. 1 to 6 are cross-sectional views of transistor cell areas of asemiconductor body at successive stages in the manufacture of atrench-gate semiconductor device according to an embodiment of theinvention;

FIG. 7 is a cross-sectional view along line A-A of the device shown inFIG. 6;

FIG. 8 is an internal plan view of the packaging of a discrete deviceembodying the invention;

FIG. 9 is an internal plan view of the packaging of a module embodyingthe invention; and

FIGS. 10 and 11 are cross-sectional views of transistor cell areas of asemiconductor body at successive stages in the manufacture of atrench-gate semiconductor device according to a further embodiment ofthe invention.

It should be noted that the Figures are diagrammatic and not drawn toscale. Relative dimensions and proportions of parts of these Figureshave been shown exaggerated or reduced in size, for the sake of clarityand convenience in the drawings. The same reference signs are generallyused to refer to corresponding or similar features in modified anddifferent embodiments.

FIG. 6 illustrates an exemplary embodiment of a power semiconductordevice in accordance with the invention. Source and drain regions 2 and4, respectively of a first conductivity type (n-type in this example)are separated by a channel-accommodating region 6 of the opposite,second conductivity type (that is, p-type in this example).

By way of example, FIG. 6 shows a vertical device structure in whichregion 4 a may be a drain drift region formed by an epitaxial layer ofhigher resistivity (lower doping) on a substrate, drain contact region 4b of relatively high conductivity. The drain drift and contact regions 4a and 4 b form a junction 4 c therebetween. The drain contact region 4 bmay be of the same conductivity type (n-type in this example) as theregion 4 a to provide a vertical MOSFET, or it may be of oppositeconductivity type (p-type in this example) to provide a vertical IGBT.

A gate 8 is present in a first trench portion 10 a which extends throughthe regions 2 and 6 and into an underlying portion of the drain driftregion 4 a. The application of a voltage signal to the gate 8 in theon-state of the device serves in known manner to induce a conductionchannel 16 in the region 6 and to control current flow in thisconduction channel 16 between the source and drain regions 2 and 4.

The source region 2 is contacted by a source electrode 18 in the case ofa MOSFET at the top major surface 20 a of the device semiconductor body20 (typically of monocrystalline silicon). The drain contact region 4 bis contacted by an electrode 22, called the drain electrode in the caseof a MOSFET, at the bottom major surface 20 b of the devicesemiconductor body 20. The source and drain electrodes 18 and 22 areknown as the emitter and collector, respectively, in an IGBT.

A field plate 24 is provided in a second trench portion 10 b, betweenthe gate 8 and the drain drift region 4 a. The field plate is preferablyformed of doped polycrystalline silicon of the first conductivity type.Alternatively, it may be made of metal, for example. The field plate 24is insulated from the surrounding semiconductor body 20 by a field plateinsulating layer 26 b. The gate 8 is insulated from the field plate 24,the semiconductor body 20, and the source electrode 28 by gateinsulating layer 26 a. This layer may consist of silicon dioxide, forexample.

In the embodiment shown in FIG. 6, the second trench portion 10 bextends into the semiconductor body 20 to a depth close to the junction4 c between the drain drift and contact regions, 4 a and 4 b. As is wellknown in the art, in practice, there is a doping transition regionbetween regions 4 a and 4 b, as there is dominant diffusion of dopantatoms from the more highly doped drain contact region into the draindrift region. Typically, this out-diffusion extends 1 to 1.5 micronsabove the junction 4 c. Preferably, the second trench portion 10 bextends to a depth immediately above the transition region.

The field plate 24 is spaced from the bottom and sidewalls of the secondtrench portion 10 b by a layer of insulating material 26 b of thicknesst1. The gate 8 is spaced from the semiconductor body and the field plateby a layer of insulating material of thickness t2. Thickness t2 may beof the order of 38 nm, whilst t1 may be of the order of 0.4 micron, forexample. A relatively thick layer is desirable below the field plate(ie. t1), particularly for higher levels of doping in the drain driftregion 4 a, so that it is able to withstand the high electric fieldsproduced at the corners of the trench.

FIG. 7 shows a cross-section through the device of FIG. 6, along lineA-A. It illustrates an example of how a connection to the field plate 24may be made from outside the semiconductor body 20, independently of thegate and source electrodes.

Doped polycrystalline silicon contact layer 39 is provided towards oneend of the first trench portion 10 a and is electrically connected tothe field plate 24. It extends from the field plate to the top majorsurface 20 a of the device semiconductor body 20, where it is contactedby a field plate contact electrode 41. The gate 8 is electricallyconnected to a gate contact electrode 40 towards the other end of thefirst trench portion 10 a.

Successive stages in the manufacture of the transistor cells of FIG. 6will now be described with reference to FIGS. 1 to 6.

Initially, a thin layer 30 of silicon dioxide is grown on the top majorsurface 20 a of the semiconductor body 20 (FIG. 1). Mask 32 is providedthereover, which may be formed in a standard manner usingphotolithography and etching. The mask may be formed of photoresist forexample, and defines windows 32 a.

An etching treatment is now carried out at the windows 32 a of the mask32 to form first grooves 28 a as shown in FIG. 2. A uniform layer ofsilicon nitride (for example) is then deposited and an anisotropic etchapplied to leave spacers 34 adjacent the sidewalls of the first grooves28 a (see FIG. 3). Spacers 34 in turn define windows 34 a therebetweenfor a further etching treatment to form second grooves 28 b which extenddown into the semiconductor body from the bottom of the first grooves 28a.

Next, as illustrated in FIG. 4, an oxidation process is carried out toform oxide layer 26 b at the bottom and sidewalls of the second grooves28 b. Preferably, a thermal oxidation is performed. This consumessilicon at these surfaces, and the resulting layer extends approximatelyequal distances away from the plane of the original silicon surfaces.For example, the oxide may be grown 0.2 microns in each direction, toform a layer 0.4 microns thick. The boundary between field plateinsulating layer 26 b and the semiconductor body 20 defines a secondtrench portion 10 b of the finished device, whilst first groove 28 adefines a first, wider trench portion 10 a. Doped polycrystallinesilicon is then deposited in a known manner and then etched back, untilthe material is only left in the space surrounded on three sides by theinsulating layer 26 b, to form field plate 24. The endpoint of thisetching step is clearly defined, as at this point, the insulating layer26 b is exposed as the polycrystalline silicon is etched back level withthe bottom of the first trench portion. Refractive monitoring forexample may be used to detect exposure of the upper surface of theinsulating layer 26 b.

Although the first trench portion 10 a is wider than the second trenchportion 10 b in the embodiment of FIG. 4, it will be appreciated thatthe process described may be carried out such that the first and secondportions 10 a and 10 b are substantially the same width.

The spacers 34 are then removed, for example, by a spray etch process. Athin gate insulating layer 26 a is subsequently deposited over thesidewalls and bottom of the first trench portion 10 a, and also over theexposed upper surface of the field plate 24. A second sequence ofdeposition and etch back of doped polycrystalline silicon is nextcarried out to form a gate 8 in the first trench portion 10 a, as shownin FIG. 5.

Further processing is carried out in a known manner to form implantedsource region 2 and channel-accommodating region 6, an insulating cap 38over the gate 8, and source and drain electrodes 18, 22 over the top andbottom major surfaces 20 a, 20 b of the semiconductor body,respectively, to form the structure illustrated in FIG. 6.

As noted in U.S. Pat. No. 5,998,833 and EP-A-1170803, the inclusion of atrenched field plate connected to the source region in a trench-gatedevice is beneficial for the device performance. Furthermore, theinventors have found that application of a bias potential to the fieldplate greater than the gate potential and near to the bulk breakdownvoltage of the drain drift region affords further performanceimprovements In particular, a bias potential around 60 to 100% of thebulk breakdown voltage of the drain drift region is preferable. Moreparticularly, a bias potential of around 80% of the bulk breakdownvoltage of the drain drift region is preferred, as it allows sometolerance of variations in the width of the transition region betweenthe drain drift and contact regions which may lead to variations in thelevel of doping in the drain drift region around the bottom of thetrench.

FIG. 8 shows an internal plan view of the packaging of a discrete devicein accordance with an embodiment of the invention. A MOSFET die 40 has agate bond pad 42 connected to its gate contact electrode, a source bondpad 48 connected to its source contact electrode, and a field plate bondpad 44 connected to its field plate contact electrode for applying anindependent bias thereto. The MOSFET is mounted on a drain pad 46, whichis electrically connected to the drain electrode 22 on the bottom majorsurface of the MOSFET die. Bond wires 50 connect the bond pads 42, 44,48 to respective terminals or pins 52, 54 and 58. Drain pad 46 directlycontacts the respective pin 56. The packaging may be completed in aknown manner.

In preferred embodiments of the invention, a semiconductor device asdescribed above is included in a module, with its field plate(s)connected to an internal voltage line or level of the module. As anexample of this, FIG. 9 shows an internal plan view of the packaging ofa module 60 including two semiconductor devices having biased fieldplates of the form described above. The module is a DC-DC converter, foruse as a VRM in a PC motherboard, for example. A known DC-DC convertercircuit and its operation are described in U.S. Pat. No. 6,175,225 ofthe present applicant (our ref. PHB34370), the contents of which arehereby incorporated herein as reference material. The configurationshown in FIG. 9 is a modified implementation of the circuit shown inFIG. 3 of U.S. Pat. No. 6,175,225.

The module of FIG. 9 includes a control MOSFET 62, a “sync” MOSFET 64,and a driver IC 66. The MOSFETs correspond to first and second switches5 and 6 of FIG. 3 of U.S. Pat. No. 6,175,225, respectively. They areconnected in series between a DC input, V_(DD), and ground, V_(SS). Theswitches are closed alternately in response to a switching signal,PWM_(IN), which is inputted to driver IC 66. The further operation of acircuit of this type is described in U.S. Pat. No. 6,175,225.

In accordance with the present invention, each MOSFET 62, 64 includes afield plate bond pad 68 which is connected to the respective field platecontact electrode of each MOSFET. The field plate bond pad of syncMOSFET 64 is connected to the power supply voltage, V_(CC), via thedriver IC, for example, which may typically be 5 or 12V. In the circuitshown in FIG. 3 of U.S. Pat. No. 6,175,225, the gate drive to thecontrol MOSFET (“first switch 5”) is via a boost or reservoir capacitor37 connected between a boost terminal 33 and Vout. In this case, thefield plate bond pad of control MOSFET 62 would be connected to boostterminal 33.

In an example where V_(CC) is 12V, the silicon selected for the MOSFETs62 and 64 may have a bulk breakdown voltage of around 15V or more, forexample.

It will be appreciated that other potentials may be provided in a modulefor connection to the field plate bond pad of a MOSFET, for example viaan external pin of the module or by including additional circuitrywithin the module.

Low doped drain drift region 4 a may typically be grown as an epitaxiallayer of the first conductivity type. The doping concentration of thedrift region may be substantially uniform throughout its depth.Nevertheless, it may be preferable to vary the concentration across thedrift region. In particular, providing a doping profile with theconcentration decreasing (for example in a linear manner) in thedirection from the drain contact region 4 b towards thechannel-accommodating region 6 may reduce the on-resistance of thedevice.

The process described above with respect to FIGS. 1 to 6 may be modifiedin a further embodiment of the invention. In particular, after growth ofthe field plate insulating layer 26 b as described in relation to FIG. 4above, the spacers 34 may be removed, and a gate insulating layer 26 a′deposited (or may be thermally grown) over the sidewalls and bottom ofthe first trench portion 10 a, before deposition of electrode materialto fill both the first and second trench portions 10 a, 10 b, as shownin FIG. 10. The electrode material is planarised level with the silicondioxide layer 30 on the top major surface 20 a of the semiconductor body20. Thus, in this embodiment, field plate 24 is integral with the gate8. Provision of a field plate at gate potential which extends into thedrain drift region improves the breakdown characteristics of the device.

Then in a similar manner to the embodiment of FIGS. 1 to 6, furtherprocessing is carried out in a known manner to form implanted sourceregion 2 and channel-accommodating region 6, an insulating cap 38 overthe gate 8, and source and drain electrodes 18, 22 over the top andbottom major surfaces 20 a, 20 b of the semiconductor body,respectively, to form the structure illustrated in FIG. 11.

It will be evident that many variations and modifications are possiblewithin the scope of the invention. The particular examples describedabove are n-channel devices, in which the source and drain regions 2 and4 are of n-type conductivity, the channel-accommodating body region 6 isof p-type conductivity, and an electron inversion channel 16 is inducedin the region 6 by the gate 8. By using opposite conductivity typedopants, a p-channel device can be made. In that case, regions 2 and 4are of p-type, the region 6 is of n-type, and a hole inversion channelis induced in the region 6 by the gate 8.

Furthermore, a device may be manufactured in accordance with theinvention of the p-channel type, having p-type source and drain regions2 and 4, and a p-type channel-accommodating region 6. It may also havean n-type deep localised region within each cell. N-type polycrystallinesilicon may be used for the gate 8. In operation, a hole accumulationchannel 16 is induced in the region 6 by the gate 8 in the on-state. Thelow-doped p-type region 6 may be wholly depleted in the off-state, bydepletion layers from the insulated gate 8 and from the deep n-typeregion.

A vertical discrete device has been illustrated with reference to FIGS.1 to 7, having its drain electrode 22 contacting the region 4 b at theback surface 20 b of the body 20. However, an integrated device is alsopossible in accordance with the invention. In this case, the region 4 bmay be a doped buried layer between a device substrate and the epitaxiallow-doped drain region 4 a. This buried layer region 4 b may becontacted by an electrode at the front major surface 20 a, via a dopedperipheral contact region which extends from the surface 20 a to thedepth of the buried layer.

Semiconductor materials other than silicon may be used for devices inaccordance with the invention, for example, silicon carbide.

No plan view of the cellular layout geometry for a vertical device isshown in the drawings, because the invention is applicable to quitedifferent, known cell geometries. Thus, for example the cells may have asquare geometry, or they may have a close-packed hexagonal geometry oran elongate stripe geometry. In each case, the trench 10 (with its gate8) extends around the boundary of each cell. FIGS. 1 to 7 shows only twocells, but typically the device comprises many hundreds of theseparallel cells between the electrodes 18 and 22. Similarly, only onecell is shown in FIG. 6 for the purposes of illustration.

The active cellular area of the device may be bounded around theperiphery of the body 20 by various known peripheral termination schemes(also not shown). Such schemes normally include the formation of a thickfield-oxide layer at the peripheral area of the body surface 20 a,before the transistor cell fabrication steps. Furthermore, various knowncircuits (such as gate-control circuits) may be integrated with thedevice in an area of the body 20, between the active cellular area andthe peripheral termination scheme. Typically their circuit elements maybe fabricated with their own layout in this circuit area using some ofthe same masking and doping steps as are used for the transistor cells.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the art, and which may be used instead of or inaddition to features already described herein.

Although claims have been formulated in this Application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel feature orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention.

The Applicants hereby give notice that new claims may be formulated tosuch features and/or combinations of such features during theprosecution of the present Application or of any further Applicationderived therefrom.

1. A method of manufacturing a trench-gate semiconductor device, thedevice having a semiconductor body defining a first portion of a trenchhaving an insulated gate therein, a second portion of the trenchextending from the bottom of the first trench portion, thesemiconductor: body comprising a source region and a drain region of afirst conductivity type which are separated by a channel-accommodatingregion adjacent to the first trench portion, the drain region comprisinga drain drift region and a drain contact region, with the drain driftregion between the channel-accommodating region and the drain contactregion, and the drain drift region doped to a lesser extent than thedrain contact region, and a field plate in the second portion of thetrench between the gate and the drain contact region, the methodcomprisinging the steps of: (a) etching a first groove into thesemiconductor body; (b) forming spacers adjacent the sidewalls of thefirst groove which define a window therebetween; (c) etching a secondgroove into the semiconductor body through the window between thespacers, the second groove extending from the bottom of the first groovetowards the drain contact region and being narrower than the firstgroove; and (d) forming a field plate insulating layer by oxidising thebottom and sidewalls of the second groove; (e) providing the field plateover the field plate insulating layer in the second groove by fillingthe first and second grooves with electrode material, and etching itback until the field plate insulating layer is exposed; (f) removing thespacers; (g) forming a gate insulating layer over the field plate and atthe bottom and sidewalls of the first groove; and (h) providing the gateover the gate insulating layer.
 2. The method as recited in claim 1,further comprising the steps of: (i) removing the spacers; (j) forming agate insulating layer over the bottom and sidewalls of the first grooveand then (k) filling the first and second grooves with electrodematerial to form the gate and field plate.
 3. A trench-gatesemiconductor device manufactured according to the method of claim 1,wherein the width of the first trench portion is greater than the widthof the second trench portion.
 4. A trench-gate semiconductor devicemanufactured according to the method of claim 1 wherein the field plateis connected to the source region.
 5. A trench-gate semiconductor devicemanufactured according to the method of claim 1 wherein the field plateis connected to a bias potential greater than the gate potential andnear to the bulk breakdown voltage of the drain drift region.
 6. Amodule comprising a trench-gate semiconductor device as-recited in claim5 wherein the field plate is connected to an internal voltage line ofthe module.
 7. The trench-gate semiconductor device as recited in claim5, wherein an additional external terminal is provided which iselectrically connected to the field plate.
 8. The trench-gatesemiconductor device as recited in claim 5, wherein the bias potentialis around 60 to 100% of the bulk breakdown voltage of the drain driftregion.
 9. The trench gate semiconductor device as recited in claim 8,wherein the bias potential is around 80% of the bulk breakdown voltageof the drain drift region.
 10. The module as recited in claim 6, whereinan additional external terminal is provided which is electricallyconnected to the field plate.
 11. The module as recited in claim 6,wherein the bias potential is around 60 to 100% of the bulk breakdownvoltage of the drain drift region.
 12. The trench-gate semiconductordevice as recited in claim 7, wherein, the bias potential is around 60to 100% of the bulk breakdown voltage of the drain drift region.